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{{tag>collection_pbx vendor_dec type_unknown year_1981 foundry_unknown}}
VAX-11/750 DC608 ALP Arithmetic and Logic Processor.

This is a DEC chip and as such is known under multiple IDs:
<code>
Schematic        : ALP
Schematic        : DC608B
Package          : 608B
Package          : 19-14682-00
Bill of Materials: 1914682-00
</code>

Implements the ALU, last level shifter and Q,D registers in the 11/750 data path.

Built on the DC600 gate array, providing 400 4-input STTL NAND gates.

Technology specifications per EK-KA750-TD-002 (CPU Technical Description):
<code>
    Implementation Technique - Gate Arrays
    Circuit Technology       - Low-Power Bipolar Schottky
    Circuit Density          - Large Scale Integration (LSI)
    
    Die Size                 - .215 in x .244 in
    Power Utilized per Die   - 2 W max
    Package Size             - 1.44 in2 (2.4 in x 0.6 in)
    I/O Circuits per Die     - 44 I/O transceiver gates
    Logic Gates              - 400 identical 4-input NAND gates
    Voltage Used             - 2.5V, 5.0V
    Speed per Gate           - 5 - 10 ns
</code>


====== Package ======

{{:pbx:dec:dc608:pack_top.jpg?300|}}

<code>
</code>

{{:pbx:dec:dc608:pack_btm.jpg?300|}}

<code>
</code>

The package is an odd pinless version of a 48-pin sidebraze CERDIP.
In the machine the die faces towards the PCB and a heatsink is attached to the top of the package (facing the back of die).

{{:pbx:dec:dc613:pack_perspective.jpg?300|}}


====== Die ======

<code>
DC600
DC608

XSC2594A
</code>

{{https://siliconprawn.org/map/dec/dc608/single/dec_dc608_pbx_mz_neo10.thumb.jpg}}

[[https://siliconprawn.org/map/dec/dc608/pbx_mz_neo10/|mz_neo10]]

  * [[https://siliconprawn.org/map/dec/dc608/single/dec_dc608_pbx_mz_neo10.jpg|Single]] (16978x14767, 76.3744MiB)